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AT26DF081A
Figure 9-5.
C S
Read Sector Protection Register
0
1
2
3
4
5
6
7
8
9
10 11 12
2 9 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 39 40
S CK
OPCODE
ADDRE SS BIT S A2 3 -A0
S I
0
0
1
1
1
1
0
0
A
A
A
A
A
A
A
A
A
M S B
M S B
DATA BYTE
S O
HIGH-IMPEDANCE
D
D
D
D
D
D
D
D
D
D
M S B
M S B
9.7
Protected States and the Write Protect (WP) Pin
The WP pin is not linked to the memory array itself and has no direct effect on the protection sta-
tus of the memory array. Instead, the WP pin, in conjunction with the SPRL (Sector Protection
Registers Locked) bit in the Status Register, is used to control the hardware locking mechanism
of the device. For hardware locking to be active, two conditions must be met – the WP pin must
be asserted and the SPRL bit must be in the logical “1” state.
When hardware locking is active, the Sector Protection Registers are locked and the SPRL bit
itself is also locked. Therefore, sectors that are protected will be locked in the protected state,
and sectors that are unprotected will be locked in the unprotected state. These states cannot be
changed as long as hardware locking is active, so the Protect Sector, Unprotect Sector, and
Write Status Register commands will be ignored. In order to modify the protection status of a
sector, the WP pin must first be deasserted, and the SPRL bit in the Status Register must be
reset back to the logical “0” state using the Write Status Register command. When resetting the
SPRL bit back to a logical “0”, it is not possible to perform a Global Protect or Global Unprotect
at the same time since the Sector Protection Registers remain soft-locked until after the Write
Status Register command has been executed.
If the WP pin is permanently connected to GND, then once the SPRL bit is set to a logical “1”,
the only way to reset the bit back to the logical “0” state is to power-cycle or reset the device.
This allows a system to power-up with all sectors software protected but not hardware locked.
Therefore, sectors can be unprotected and protected as needed and then hardware locked at a
later time by simply setting the SPRL bit in the Status Register.
When the WP pin is deasserted, or if the WP pin is permanently connected to VCC, the SPRL bit
in the Status Register can still be set to a logical “1” to lock the Sector Protection Registers. This
provides a software locking ability to prevent erroneous Protect Sector or Unprotect Sector com-
mands from being processed. When changing the SPRL bit to a logical “1” from a logical “0”, it is
also possible to perform a Global Protect or Global Unprotect at the same time by writing the
appropriate values into bits 5, 4, 3, and 2 of the Status Register.
21
3600G–DFLASH–06/09
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